1. Field of the Invention
The present invention generally relates to heat sink assemblies and, more particularly, to a technique and assembly arrangement wherein a heat sink is positioned in thermal contact with a substrate such as an integrated circuit chip or electronic package but does not impart any stressful forces on the substrate, thereby avoiding damage to interconnect both at the heat sink substrate interface and at the substrate underlying support interface.
2. Background Description
Modern integrated circuit chips, chip carriers, and other electronic substrates and the use of higher powers in these devices mandate a need for better heat dissipation schemes. Current industry solutions have included the use of active heat sinks or elaborate structures to improve the thermal load carrying capacity of select components; however, these approaches tend to add undesirable cost and complexity, and also reduce reliability of the final system design.
A simple solution appears to be the use of larger and heavier heat sinks since limitations in heat sink mass limit the range of allowable electronic package power dissipation. However, larger and heavier heat sinks have not proven effective, particularly when they are applied to surface mounted components. There are serious constraints linked to the amount of heat sink mass which can actually be supported without adversely affecting the reliability of the interconnections to surface mounted components. Large mass heat sinks cause excessive stresses to both first and second level interconnections (i.e., component to heat sink being the site of first level interconnections, and component to circuit card being the site of second level interconnections) during shipping and/or over the machine life time, resulting a degradation to interconnection geometry and subsequently package interconnection reliability.
In certain circumstances substituting pin through hole connections for surface mount structures is not a viable option. Therefore, it would be advantageous to provide an effective mechanism and methodology which allows using high mass heat sinks with surface mounted electronic packages and components.
U.S. Pat. No. 5,386,338 to Jordan et al. and U.S. Pat. No. 5,464,054 to Hinshaw et al. each show a spring clamp mechanism for securing a heat sink to a mounting frame. In operation, an electronic device package is positioned within an aperture of a mounting frame, and the heat sink is secured to the mounting frame using a spring clip which fits across the heat sink and has projecting ends which are flexed to a point underneath tab members on the mounting frame. The patents also discuss the possibility of eliminating the mounting frame and securing the projecting ends in specially designed recesses positioned outside a socket connection in a circuit board which receives the electronic package. The configurations described in Jordan and Hinshaw each require a constant spring force to be applied against the surface of the electronic package, and would be wholly inappropriate for electronic packages that use surface mount interconnections.
U.S. Pat. No. 4,885,126 to Polonio shows, in FIGS. 31 and 41, a packaging system wherein integrated circuit chips are housed in recessed regions in a housing that is connected to a printed circuit board using pin connections . A convection heat sink is bonded to the top of the housing forming a hermetic seal for the chips in the housing. However, like Jordan and Hinshaw, Polonio relies on a compressive spring force to maintain thermal contact between the chips in the housing and the heat sink. In Polonio, the spring members are positioned between the top of the integrated circuit chips and the bottom of the heat sink, and are compressed at the time of creating the hermetic seal. In addition, Polonio is not related to and does not address problems that arise with surface mount components.
U.S. Pat. No. 4,455,457, to Kurokawa discloses several different packaging arrangements for semiconductors that are designed to increase thermal dissipation. In each configuration, a chip is positioned within a recess in a housing that is equipped with pin connectors for connection to a circuit board, and a heat diffusing plate contacts the top of the chip and serves to transfer heat from the chip to a heat sink positioned on top of the housing. Kurokawa relies on an elastic bias from a metallic member positioned between the diffusing plate and the heat sink to maintain contact between the diffusing plate and the chip. The heat sink is attached directly to the heat sink. The Kurokawa reference does not discuss arrangements which would be suitable for surface mount technologies.
U.S. Pat. No. 5,311,402 to Kobayashi describes an integrated circuit device fitted inside a chip holder where the integrated circuit device is adhesively bonded to a cap, and where the cap fits within grooves on an underlying substrate. The Kobayashi patent is mainly directed to positioning a chip on a circuit board, and is not concerned with heat sinks or the adverse impact of a heavy element on interconnections when the heavy element is connected to a device or substrate.